Title: RAS Challenges & Solution for Today’s Chiplet-based Systems

Speaker: Yervant Zorian

Abstract:
RAS plays a major role in multi-die chiplet-based systems, since individual chiplets, the interconnects between them, and the final integrated system must all be of known-good quality and reliability.  So, RAS is a critical investment, if the overall design includes many different chiplets. With the growth in high-speed communication between chiplets, such as UCIe for logic-to-logic chiplets, and HBM for memory to logic chiplets, designers must be aware of test, monitoring and repair demands in all lifecycle phases by embedding corresponding resources for design-for-test, signal monitors and redundancy elements everywhere. Besides discussing this essential on-chip infrastructure, this presentation also covers silicon lifecycle management for chiplet-based systems, including the automated solutions needed to operate test and reliability sets, apply them, and perform data analytics on the results. 

Keynote

Corporate Vice President, General Manager, Data Center and AI Product Management, Intel Corporation

Dr. Zane A. Ball is a Corporate Vice President and General Manager of the Data Center and AI (DCAI) Product Management Group. DCAI Product Management is responsible for end-to-end stewardship of DCAI’s systems, SW, CPU, GPU, and custom product line through the entirety of the product lifecycle.  Prior to his product management role, Ball was CVP and GM of platform engineering and architecture for Intel’s data center business.  Ball has also served as Co-GM of Intel’s foundry effort as a VP in the Technology and Manufacturing group and VP of the Client Computing Group including roles as GM of the desktop client business and as GM of global customer engineering.

Ball has a bachelor’s degree, master’s degree, and Ph.D. in electrical engineering, all earned from Rice University.  He also holds six patents in high-speed electrical design.