Arijit Biswas is a Senior Principal Engineer in the Datacenter Products Architecture group at Intel.  He graduated from Carnegie Mellon University in 1997, joining Intel’s Pentium 4 design team immediately thereafter.  During his 25+ year career he has done everything from post-Si debug through circuit design & validation to architecture & micro-architecture.  Arijit is technical director of the Technologies for Reliability & Usage group, responsible for developing several marquee technologies such as Turbo Boost Max 3.0 and Xeon reliability architectures to mitigate soft errors & silent data errors.  Arijit developed the first architectural vulnerability factor models using analytical methods at Intel, which are now broadly used across the company as well as the industry.  In doing so he and his team developed many of the fundamental principles guiding analytical reliability modeling today such as address based AVF.  Arijit is currently the chief architect of the Sapphire Rapids & Emerald Rapids Xeon CPUs (4th & 5th Gen Intel Xeon CPUs).

Keynote

Corporate Vice President, General Manager, Data Center and AI Product Management, Intel Corporation

Dr. Zane A. Ball is a Corporate Vice President and General Manager of the Data Center and AI (DCAI) Product Management Group. DCAI Product Management is responsible for end-to-end stewardship of DCAI’s systems, SW, CPU, GPU, and custom product line through the entirety of the product lifecycle.  Prior to his product management role, Ball was CVP and GM of platform engineering and architecture for Intel’s data center business.  Ball has also served as Co-GM of Intel’s foundry effort as a VP in the Technology and Manufacturing group and VP of the Client Computing Group including roles as GM of the desktop client business and as GM of global customer engineering.

Ball has a bachelor’s degree, master’s degree, and Ph.D. in electrical engineering, all earned from Rice University.  He also holds six patents in high-speed electrical design.