{"id":157,"date":"2024-04-20T10:08:31","date_gmt":"2024-04-20T10:08:31","guid":{"rendered":"https:\/\/ieee-ras.conferences.computer.org\/2024\/?page_id=157"},"modified":"2024-06-10T14:08:26","modified_gmt":"2024-06-10T14:08:26","slug":"program-structure","status":"publish","type":"page","link":"https:\/\/ieee-ras.conferences.computer.org\/2024\/program-structure\/","title":{"rendered":"Program Structure"},"content":{"rendered":"\t\t
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Tuesday, 11th June 2024 (SingleTrack)<\/h2><\/h4>\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t
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Timeslot<\/strong><\/td>Topic<\/strong><\/td>Organizer<\/strong><\/td>Moderator<\/strong><\/td>Speaker<\/strong><\/td>Title<\/strong><\/td><\/tr>
7:00 \u2013 8:30<\/td>Registration and Breakfast<\/td><\/tr>
8:30 \u2013 9:00<\/td>Opening Address<\/td>Jyotika Athavale\u00a0BIO<\/strong><\/span><\/a><\/span>, Yervant Zorian BIO<\/strong><\/span><\/a><\/span>, Dimitris Gizopoulos\u00a0BIO<\/strong><\/span><\/a><\/span>, Amr Haggag (Chairs)<\/td>Welcome<\/td><\/tr>
9:00 \u2013 10:00<\/td>9:00-9:30<\/td>Keynote 1<\/td>Jyotika Athavale (IEEE Computer Society)<\/td>Ankur Garg (Microsoft) BIO<\/strong><\/a><\/span><\/td>Navigating the AI Era: The Essential Role of RAS ABSTRACT<\/strong><\/span><\/a><\/span><\/td><\/tr>
9:30-10:00<\/td>Keynote 2<\/td>Steve Hesley (AMD) BIO<\/strong><\/a><\/span><\/td>The Vital Role of RAS ABSTRACT<\/strong><\/span><\/a><\/span><\/td><\/tr>
10:00 \u2013 10:30<\/td>Coffee Break<\/td><\/tr>
10:30 \u2013 12:00<\/td>Invited Special Session 1
(SS1 Quality)<\/td>		Rama Govindaraju (Google)<\/td>Rama Govindaraju (Google)<\/td>Subhasish Mitra (Stanford)\u00a0BIO<\/strong><\/span><\/a><\/span>
Vilas Sridharan (AMD)\u00a0BIO<\/strong><\/span><\/a><\/span>
Harish Dixit (Meta)\u00a0BIO<\/strong><\/span><\/a><\/span>
David Lerner (Intel)\u00a0BIO<\/strong><\/span><\/a><\/span><\/td>

SDC (ELF and best practices for in-situ screening)<\/strong><\/span><\/p>

A Cambrian Explosion in Robust Computing Systems is Dead Ahead ABSTRACT<\/strong><\/span><\/a><\/span><\/p>

Addressing emerging fault modes with testing and reliability ABSTRACT<\/strong><\/span><\/a><\/span><\/p>

Silent Data Corruptions at Scale ABSTRACT<\/strong><\/span><\/a><\/span><\/p>

Silent Data Errors: Causes, Implications to AI Workloads, and In-Field Mitigation ABSTRACT<\/strong><\/span><\/a><\/span><\/p><\/td><\/tr>

12:00 \u2013 13:00<\/td>Lunch<\/td><\/tr>
13:00 \u2013 14:00<\/td>13:00-13:30<\/td>Keynote 3<\/td>Yervant Zorian (Synopsys)<\/td>George Tchaparian (OCP) BIO<\/strong><\/span><\/a><\/span><\/td>Challenges and OCP Community Progress towards Reliability, Availability, and Serviceability (RAS) with a Special Focus on Artificial Intelligence ABSTRACT<\/strong><\/span><\/a><\/span><\/td><\/tr>
13:30-14:00<\/td>Keynote 4<\/td>Zane Ball (Intel) BIO<\/strong><\/span><\/a><\/span><\/td>Pioneering Reliability, Availability, and Serviceability in the AI era ABSTRACT<\/strong><\/span><\/a><\/span><\/td><\/tr>
14:00 \u2013 15:30<\/td>Invited Special Session 2
(SS2 Reliability)<\/td>		Rama Bhimanadhuni (Microsoft)<\/td>Shawn Blanton (CMU)<\/td>Yogesh Varma (Intel)\u00a0BIO<\/strong><\/span><\/a><\/span>
Rama Bhimanadhuni (MSFT)\u00a0BIO<\/strong><\/span><\/a><\/span>
Drew Walton\u00a0BIO<\/strong><\/span><\/a><\/span>
Dimitris Gizopoulos (U of Athens)\u00a0BIO<\/strong><\/span><\/a><\/span><\/td>

Hardware Fault Management<\/strong><\/span><\/p>

Towards Autonomous Hardware Fault Management ABSTRACT<\/strong><\/span><\/a><\/span><\/p>

Enabling Generative AI- Exploring RAS Requirements for Hyperscale AI Infrastructure ABSTRACT<\/strong><\/span><\/a><\/span><\/p>

Efforts to Address Fault Management Challenges in OCP ABSTRACT<\/strong><\/span><\/a><\/span><\/p>

The Role of Abstraction and Modeling in the Assessment of Hardware Faults Effects ABSTRACT<\/strong><\/span><\/a><\/span><\/p><\/td><\/tr>

15:30 \u2013 16:00<\/td>Coffee Break<\/td><\/tr>
16:00 – 17:30<\/td>Invited Special Session 3
(SS3 Availability)<\/td>		Yogesh Varma (Intel)<\/td>Cecilia Metra (U of Bologna)<\/td>Swadesh Choudhary (Intel)\u00a0BIO<\/strong><\/span><\/a><\/span>
Yervant Zorian (Synopsys)\u00a0BIO<\/strong><\/span><\/a><\/span>
Arijit Biswas (Intel)\u00a0BIO<\/strong><\/span><\/a><\/span>
Sanjay Gongalore (Nvidia)\u00a0BIO<\/strong><\/span><\/a><\/span><\/td>

Pathfinding Toward SoC Self-Healing Architectur<\/strong>e<\/strong><\/span><\/p>

UCIe RAS Overview ABSTRACT<\/strong><\/span><\/a><\/span><\/p>

RAS Challenges & Solution for Today\u2019s Chiplet-based Systems ABSTRACT<\/strong><\/span><\/a><\/span><\/p>

Pathfinding Toward SoC Self-Healing Architecture ABSTRACT<\/strong><\/span><\/a><\/span><\/p>

Maximizing Availability for a Zettascale Datacenter ABSTRACT<\/strong><\/span><\/a><\/span><\/p><\/td><\/tr>

17:30 \u2013 19:00<\/td>Reception with IEEE CS BOG<\/td><\/tr>
19:00 \u2013 20:30<\/td>Invited Special Session 4
(SS4 Serviceability)<\/td>		Drew Walton<\/td>Drew Walton\u00a0<\/td>John Holm (Intel)\u00a0BIO<\/strong><\/span><\/a><\/span>
Rob Chappell (Microsoft)\u00a0BIO<\/strong><\/span><\/a><\/span>
Anil Agrawal (Meta)\u00a0BIO<\/strong><\/span><\/a><\/span>
Amit Pandey (Amazon)\u00a0BIO<\/strong><\/span><\/a><\/span><\/td>

In-fleet Serviceability<\/span><\/strong><\/p>

Enhancing Computer Serviceability Through Error Telemetry ABSTRACT<\/strong><\/span><\/span><\/a><\/p>

Challenges in Hyperscale Serviceability<\/span>\u00a0<\/span>ABSTRACT<\/strong><\/a><\/span><\/span><\/span><\/p>

In-band Error Handling requirements for RAS in hyperscale data centers ABSTRACT<\/strong><\/span><\/span><\/a><\/span><\/p>

Addressing Serviceability throughout device lifecycle with High Speed Access for Test ABSTRACT<\/strong><\/span><\/a><\/span><\/p><\/td><\/tr><\/tbody><\/table>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t

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Wednesday, 12th June 2024 (Dual Track)<\/h2>\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t
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07:00 \u2013 08:00<\/p><\/td>

Breakfast<\/strong><\/p><\/td>

\u00a0<\/strong><\/p><\/td><\/tr>

\u00a0<\/p><\/td>

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\u00a0<\/strong><\/p><\/td><\/tr>

08:00 \u2013 09:15<\/p><\/td>

Session 1
Data Center RAS 1<\/strong><\/p><\/td>

Session 2<\/strong><\/p>

Memory and Interconnects 1<\/strong><\/p><\/td><\/tr>

\u00a0<\/p><\/td>

1.1 \u2013 <\/strong>Silent Data Corruption \u2013 Intel-Meta joint collaboration to detect and mitigate at-scale<\/strong><\/p>

Shubhada Sahasrabudhe, Harish Dixit, David Lerner, Tejasvi Chakravarthy, Thiago Maceira, Matt Beadon, Sriram Sankar and Ethan Hansen (Intel and Meta)\u00a0\u00a0\u00a0\u00a0\u00a0<\/p><\/td>

2.1 \u2013 <\/strong>AI in BMC: Improving DDR5 Memory Reliability in Hyperscale Data Centers <\/strong><\/p>

Shen Zhou, Dahai Zhou, Gaoyu Ruan, Zhibing Li, Yi Li and Keke Xie (Intel and Alibaba)\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0<\/p><\/td><\/tr>

\u00a0<\/p><\/td>

1.2 \u2013 <\/strong>Silent Data Corruption – Meta-AMD silent error collaboration for screening efficiency at-scale<\/strong><\/p>

Tejasvi Chakravarthy, Sankarnarayanan Gurumurthy, Harish Dattatreya Dixit and Abishek Hariharan (Meta and AMD)<\/p><\/td>

2.2 \u2013 <\/strong>The Future is Now: Empowering DRAM ECC through a Forgotten Coding Theory<\/strong><\/p>

Kelly Fitzpatrick, Saeed Raja, Yang Liu and Tong Zhang (ScaleFlux)<\/p><\/td><\/tr>

\u00a0<\/p><\/td>

1.3 \u2013 <\/strong>RAS Significance and Challenges in Hyper-Scalar Data Centers with Need for Industry Standardization<\/strong><\/p>

Tulika Jha, Bob Krick, John Lee and Saurabh Agrawal (Microsoft)<\/p><\/td>

2.3 \u2013 <\/strong>Standardized RAS API using CXL Component Command Interface<\/strong><\/p>

Shubhada Pugaonkar and Antonio Hasbun Marin (Intel)<\/p><\/td><\/tr>

\u00a0<\/p><\/td>

1.4 \u2013 <\/strong>Innovative Approaches to Solving Flash-Induced Latencies in Hyperscale Environments<\/strong><\/p>

Vineet Parekh, Suman Gumudaveli and Venkat Ramesh (Meta)<\/p><\/td>

2.4 \u2013 <\/strong>Reducing Memory Errors On-the-fly with Prediction-Guided Failure Prevention<\/strong><\/p>

Shen Zhou, Yu Zhang, Chenchen Li, Linlin Han and Feng Xu (Intel and ByteDance)<\/p><\/td><\/tr>

\u00a0<\/p><\/td>

1.5 \u2013 <\/strong>Open Compute Project’s Server Resilience Specification 1.0<\/strong><\/p>

Thiago Macieira (Intel)<\/p><\/td>

2.5 \u2013 <\/strong>PCIe Error Handling Challenges in building AI\/ML systems in hyperscale datacenters<\/strong><\/p>

Anil Agrawal and Bill Holland (Meta)<\/p><\/td><\/tr>

\u00a0<\/p><\/td>

\u00a0<\/strong><\/p><\/td>

\u00a0<\/strong><\/p><\/td><\/tr>

09:15 \u2013 10:30<\/p><\/td>

Session 3<\/strong><\/p>

Data Center RAS 2<\/strong><\/p><\/td>

Session 4<\/strong><\/p>

Memory and Interconnects 2<\/strong><\/p><\/td><\/tr>

\u00a0<\/p><\/td>

3.1 \u2013 <\/strong>OpenDCDiag: A Scalable Open-Source Solution to Search for Silent Data Errors<\/strong><\/p>

Thiago Macieira (Intel)<\/p><\/td>

4.1 \u2013 <\/strong>RAIDDR: Error Correction for Multi-device Busses<\/strong><\/p>

Majid Nemati, Terry Grunzke, Brett Dodds and Adam Grenzebach (Microsoft)<\/p><\/td><\/tr>

\u00a0<\/p><\/td>

3.2 \u2013 <\/strong>Writing SDE-finding tests using OpenDCDiag<\/strong><\/p>

Rohit Agashe and Thiago Macieira (Intel)<\/p><\/td>

4.2 \u2013 <\/strong>CXL RAS learnings<\/strong><\/p>

Manjunaatha Harapanahalli, Erwin Tsaur and Mahesh Natu (Intel)<\/p><\/td><\/tr>

\u00a0<\/p><\/td>

3.3 \u2013 <\/strong>Maintaining data integrity during transformation<\/strong><\/p>

Smita Kumar, Patrick Fleming, Gordon McFadden and Sailesh Bissessur (Intel)<\/p><\/td>

4.3 \u2013 <\/strong>Data Centers\u2019 Reliability Risks due to Faults\u00a0 Affecting their High Performance Microprocessors\u2019 Caches<\/strong><\/p>

Martin Omana, Annalisa Manfredi, Cecilia Metra, Riccardo Locatelli, Monia Chiavacci and Stefano Petrucci (U Bologna, Intel)<\/p><\/td><\/tr>

\u00a0<\/p><\/td>

3.4 \u2013 <\/strong>Microarchitectural Modeling of Modern CPUs for SDCs Prediction in Data Centers<\/strong><\/p>

Dimitris Gizopoulos, George Papadimitriou and Odysseas Chatzopoulos (U Athens)\u00a0<\/p><\/td>

4.4 \u2013 <\/strong>The Management Era: Predictive DRAM Fault Analysis with Architecture Awareness<\/strong><\/p>

Hoiju Chung, Yongjun Lee, Woongju Jang, Euisang Oh, Sanghwan Lee, Paul Fahey, Kijoong Choi, Arhatha Bramhanand and Brett Dodds (SK Hynix and Microsoft)<\/p><\/td><\/tr>

\u00a0<\/p><\/td>

3.5 \u2013 <\/strong>The Challenges of Operating a Heterogeneous Edge Cluster<\/strong><\/p>

Nicolas Oliver, Rajkumar Patel, Dean Throop and Mrinal Karvir (Intel)<\/p><\/td>

4.5 \u2013 <\/strong>Managing Memory Correctable Error Solutions<\/strong><\/p>

Shawn Fan, Alex Zhou, Eric Li, Annie Yu, Taniya Siddiqua, Kaushik Balasubramanian, Fang Yuan and Xiaoguo Liang (Intel and Tencent)<\/p><\/td><\/tr>

\u00a0<\/p><\/td>

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10:30 \u2013 11:00<\/p><\/td>

Coffee Break<\/strong><\/p><\/td>

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11:00 \u2013 12:30<\/p><\/td>

Session 5<\/strong><\/p>

AI and RAS<\/strong><\/p><\/td>

Session 6<\/strong><\/p>

Testing and Resilience<\/strong><\/p><\/td><\/tr>

\u00a0<\/p><\/td>

5.1 \u2013 <\/strong>Meta AI Server Reliability Dimensional Analysis<\/strong><\/p>

Peng Xiao and Mihir Patel (Meta)<\/p><\/td>

6.1 \u2013 <\/strong>Delay Monitoring Under Different PVT Corners<\/strong><\/p>

Hari Addepalli, Jiezhong Wu, Nilanjan Mukherjee, Irith Pomeranz and Janusz Rajski (Purdue U and Siemens)<\/p><\/td><\/tr>

\u00a0<\/p><\/td>

5.2 \u2013 <\/strong>Comprehensive Reliability Analysis in AI systems<\/strong><\/p>

Anju John, Matt Bergeron and Mihir Patel (Meta)<\/p><\/td>

6.2 \u2013 <\/strong>Timing-Verification Test for Timing Related Defects<\/strong><\/p>

Jiezhong Wu, Hari Addepalli, Nilanjan Mukherjee, Irith Pomeranz, Kun-Han Tsai and Janusz Rajski (Purdue U and Siemens)<\/p><\/td><\/tr>

\u00a0<\/p><\/td>

5.3 \u2013 <\/strong>Build High Reliability\/Availability\/Serviceability head node for AI server<\/strong><\/p>

Alex Zhou, Yu Zhang, Chenchen Li, Fang Yuan, Shijian Ge, Albert Hu, Liang Peng, Antonio J Hasbun Marin and Shawn Fan (Intel and ByteDance)<\/p><\/td>

6.3 \u2013 <\/strong>A Functionally-Aware Scan-Based Test Solution for Silent Data Corruption<\/strong><\/p>

Irith Pomeranz and Yervant Zorian (Purdue U and Synopsys)<\/p><\/td><\/tr>

\u00a0<\/p><\/td>

5.4 \u2013 <\/strong>PVF (Parameter Vulnerability Factor): A Scalable Metric to Quantify AI Vulnerability to Parameter Corruptions<\/strong><\/p>

Xun Jiao, Fred Lin and Harish Dixit (Meta)<\/p><\/td>

6.4 \u2013 <\/strong>ResGNN: A Generic Framework for Measuring Graph Neural Network Resilience Against Faults and Attacks in Hardware Systems<\/strong><\/p>

Hanqiu Chen, Zishen Wan and Cong Hao (Georgia Tech)\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0<\/p><\/td><\/tr>

\u00a0<\/p><\/td>

5.5 \u2013 <\/strong>What does measuring resilience in AI systems entail?<\/strong><\/p>

Chitkala Sethuraman (Microsoft)\u00a0\u00a0\u00a0<\/p><\/td>

\u00a0<\/p><\/td><\/tr>

\u00a0<\/p><\/td>

5.6 \u2013 <\/strong>Dual Transformer Encoding: Remaining Useful Life Estimation through Channel-Independent and Collective Approach<\/strong><\/p>

Paul Nikolian and Fadi Kurdahi (UC Invine)<\/p><\/td>

\u00a0<\/p><\/td><\/tr>

\u00a0<\/p><\/td>

\u00a0<\/p><\/td>

\u00a0<\/p><\/td><\/tr>

12:30 \u2013 14:00<\/p><\/td>

Networking Lunch<\/strong><\/p><\/td>

\u00a0<\/p><\/td><\/tr><\/tbody><\/table>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t

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Wednesday, 12th June 2024 (Dual Track)<\/h2>\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t
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07:00 \u2013 08:00<\/p><\/td>

Breakfast<\/strong><\/p><\/td>

\u00a0<\/strong><\/p><\/td><\/tr>

\u00a0<\/td>

\u00a0(Speaker Name Highlighted<\/em><\/strong>)<\/p><\/td>

\u00a0<\/strong><\/p><\/td><\/tr>

08:00 \u2013 09:15<\/p><\/td>

Session 1<\/strong><\/p>

Data Center RAS 1<\/strong><\/p>

Moderator: <\/strong>Bharath Parthasarathy<\/p><\/td>

Session 2<\/strong><\/p>

Memory and Interconnects 1<\/strong><\/p>

Moderator: <\/strong>Kwabena Boateng<\/p><\/td><\/tr>

\u00a0<\/td>

1.1 \u2013 <\/strong>Silent Data Corruption \u2013 Intel-Meta joint collaboration to detect and mitigate at-scale<\/strong><\/p>

Shubhada Sahasrabudhe, Harish Dixit, David Lerner<\/em><\/strong>, Tejasvi Chakravarthy, Thiago Maceira, Matt Beadon, Sriram Sankar and Ethan Hansen (Intel and Meta)\u00a0\u00a0\u00a0\u00a0\u00a0<\/p><\/td>

2.1 \u2013 <\/strong>AI in BMC: Improving DDR5 Memory Reliability in Hyperscale Data Centers <\/strong><\/p>

Shen Zhou, Dahai Zhou, Haoyu Ruan, Zhibing Li, Yi Li, Keke Xie, and Yogesh Varma<\/em><\/strong> (Intel and Alibaba)\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0<\/p><\/td><\/tr>

\u00a0<\/td>

1.2 \u2013 <\/strong>Silent Data Corruption – Meta-AMD silent error collaboration for screening efficiency at-scale<\/strong><\/p>

Gautham Vunnam, Abishek Hariharan<\/em><\/strong>, Sankarnarayanan Gurumurthy, Tejasvi Chakravarthy, Harish Dattatraya Dixit (Meta and AMD)<\/p><\/td>

2.2 \u2013 <\/strong>The Future is Now: Empowering DRAM ECC through a Forgotten Coding Theory<\/strong><\/p>

Kelly Fitzpatrick, Saeed Raja, Yang Liu and Tong Zhang<\/strong><\/em> (ScaleFlux)<\/p><\/td><\/tr>

\u00a0<\/td>

1.3 \u2013 <\/strong>RAS Significance and Challenges in Hyper-Scalar Data Centers with Need for Industry Standardization<\/strong><\/p>

Tulika Jha<\/em><\/strong>, Bob Krick, John Lee and Saurabh Agrawal (Microsoft)<\/p><\/td>

2.3 \u2013 <\/strong>Standardized RAS API using CXL Component Command Interface<\/strong><\/p>

Shubhada Pugaonkar<\/em><\/strong> and Antonio Hasbun Marin (Intel)<\/p><\/td><\/tr>

\u00a0<\/td>

1.4 \u2013 <\/strong>Innovative Approaches to Solving Flash-Induced Latencies in Hyperscale Environments<\/strong><\/p>

Vineet Parekh<\/em><\/strong>, Suman Gumudaveli and Venkat Ramesh (Meta)<\/p><\/td>

2.4 \u2013 <\/strong>Reducing Memory Errors On-the-fly with Prediction-Guided Failure Prevention<\/strong><\/p>

Shen Zhou, Yu Zhang, Chenchen Li<\/em><\/strong>, Linlin Han and Feng Xu (Intel and ByteDance)<\/p><\/td><\/tr>

\u00a0<\/td>

1.5 \u2013 <\/strong>Open Compute Project’s Server Resilience Specification 1.0<\/strong><\/p>

Thiago Macieira<\/em><\/strong> (Intel)<\/p><\/td>

2.5 \u2013 <\/strong>PCIe Error Handling Challenges in building AI\/ML systems in hyperscale datacenters<\/strong><\/p>

Anil Agrawal and Bill Holland<\/em><\/strong> (Meta)<\/p><\/td><\/tr>

\u00a0<\/td>

\u00a0<\/strong><\/p><\/td>

\u00a0<\/strong><\/p><\/td><\/tr>

09:15 \u2013 10:30<\/p><\/td>

Session 3<\/strong><\/p>

Data Center RAS 2<\/strong><\/p>

Moderator: <\/strong>Harish Dixit<\/p><\/td>

Session 4<\/strong><\/p>

Memory and Interconnects 2<\/strong><\/p>

Moderator: <\/strong>Sreejit Chakravarty<\/p><\/td><\/tr>

\u00a0<\/td>

3.1 \u2013 <\/strong>OpenDCDiag: A Scalable Open-Source Solution to Search for Silent Data Errors<\/strong><\/p>

Thiago Macieira<\/em><\/strong> (Intel)<\/p><\/td>

4.1 \u2013 <\/strong>RAIDDR: Error Correction for Multi-device Busses<\/strong><\/p>

Majid Nemati<\/em><\/strong>, Terry Grunzke, Brett Dodds and Adam Grenzebach (Microsoft)<\/p><\/td><\/tr>

\u00a0<\/td>

3.2 \u2013 <\/strong>Writing SDE-finding tests using OpenDCDiag<\/strong><\/p>

Rohit Agashe<\/em><\/strong> and Thiago Macieira (Intel)<\/p><\/td>

4.2 \u2013 <\/strong>CXL RAS learnings<\/strong><\/p>

Manjunaatha Harapanahalli<\/em><\/strong>, Erwin Tsaur and Mahesh Natu (Intel)<\/p><\/td><\/tr>

\u00a0<\/td>

3.3 \u2013 <\/strong>Maintaining data integrity during transformation<\/strong><\/p>

Smita Kumar, Patrick Fleming, Gordon McFadden and Sailesh Bissessur<\/em><\/strong> (Intel)<\/p><\/td>

4.3 \u2013 <\/strong>Data Centers\u2019 Reliability Risks due to Faults\u00a0 Affecting their High Performance Microprocessors\u2019 Caches<\/strong><\/p>

Martin Omana, Annalisa Manfredi, Cecilia Metra<\/em><\/strong>, Riccardo Locatelli, Monia Chiavacci and Stefano Petrucci (U Bologna, Intel)<\/p><\/td><\/tr>

\u00a0<\/td>

3.4 \u2013 <\/strong>Microarchitectural Modeling of Modern CPUs for SDCs Prediction in Data Centers<\/strong><\/p>

Dimitris Gizopoulos<\/em><\/strong>, George Papadimitriou and Odysseas Chatzopoulos (U Athens)\u00a0<\/p><\/td>

4.4 \u2013 <\/strong>The Management Era: Predictive DRAM Fault Analysis with Architecture Awareness<\/strong><\/p>

Hoiju Chung<\/em><\/strong>, Yongjun Lee, Woongju Jang, Euisang Oh, Sanghwan Lee, Paul Fahey, Kijoong Choi, Arhatha Bramhanand and Brett Dodds (SK Hynix and Microsoft)<\/p><\/td><\/tr>

\u00a0<\/td>

3.5 \u2013 <\/strong>The Challenges of Operating a Heterogeneous Edge Cluster<\/strong><\/p>

Nicolas Oliver<\/em><\/strong>, Rajkumar Patel, Dean Throop and Mrinal Karvir (Intel)<\/p><\/td>

4.5 \u2013 <\/strong>Managing Memory Correctable Error Solutions<\/strong><\/p>

Shawn Fan, Alex Zhou, Eric Li, Annie Yu, Zengping Xu<\/em><\/strong>, Taniya Siddiqua, Kaushik Balasubramanian, Fang Yuan and Xiaoguo Liang (Intel and Tencent)\u00a0<\/p><\/td><\/tr>

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10:30 \u2013 11:00<\/p><\/td>

Coffee Break<\/strong><\/p><\/td>

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11:00 \u2013 12:30<\/p><\/td>

Session 5<\/strong><\/p>

AI and RAS<\/strong><\/p>

Moderator: <\/strong>Preeti Chauhan<\/p><\/td>

Session 6<\/strong><\/p>

Testing and Resilience<\/strong><\/p>

Moderator: <\/strong>Chris Connor<\/p><\/td><\/tr>

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5.1 \u2013 <\/strong>Meta AI Server Reliability Dimensional Analysis<\/strong><\/p>

Peng Xiao<\/em><\/strong> and Mihir Patel (Meta)<\/p><\/td>

6.1 \u2013 <\/strong>Delay Monitoring Under Different PVT Corners<\/strong><\/p>

Hari Addepalli, Jiezhong Wu, Nilanjan Mukherjee<\/em><\/strong>, Irith Pomeranz and Janusz Rajski (Purdue U and Siemens)<\/p><\/td><\/tr>

\u00a0<\/td>

5.2 \u2013 <\/strong>Comprehensive Reliability Analysis in AI systems<\/strong><\/p>

Anju John<\/em><\/strong>, Matt Bergeron and Mihir Patel (Meta)<\/p><\/td>

6.2 \u2013 <\/strong>Timing-Verification Test for Timing Related Defects<\/strong><\/p>

Jiezhong Wu, Hari Addepalli, Nilanjan Mukherjee, Irith Pomeranz, Kun-Han Tsai and Janusz Rajski<\/em> <\/strong>(Purdue U and Siemens)<\/p><\/td><\/tr>

\u00a0<\/td>

5.3 \u2013 <\/strong>Build High Reliability\/Availability\/Serviceability head node for AI server<\/strong><\/p>

Alex Zhou, Yu Zhang, Chenchen Li, Fang Yuan, Shijian Ge<\/em><\/strong>, Albert Hu, Liang Peng, Antonio J Hasbun Marin and Shawn Fan (Intel and ByteDance)<\/p><\/td>

6.3 \u2013 <\/strong>A Functionally-Aware Scan-Based Test Solution for Silent Data Corruption<\/strong><\/p>

Irith Pomeranz<\/em><\/strong> (Purdue U)<\/p><\/td><\/tr>

\u00a0<\/td>

5.4 \u2013 <\/strong>PVF (Parameter Vulnerability Factor): A Scalable Metric to Quantify AI Vulnerability to Parameter Corruptions<\/strong><\/p>

Xun Jiao<\/em><\/strong>, Fred Lin and Harish Dixit (Meta)<\/p><\/td>

6.4 \u2013 <\/strong>ResGNN: A Generic Framework for Measuring Graph Neural Network Resilience Against Faults and Attacks in Hardware Systems<\/strong><\/p>

Hanqiu Chen<\/em><\/strong>, Zishen Wan and Cong Hao (Georgia Tech)\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0<\/p><\/td><\/tr>

\u00a0<\/td>

5.5 \u2013 <\/strong>What does measuring resilience in AI systems entail?<\/strong><\/p>

Chitkala Sethuraman<\/em><\/strong> (Microsoft)\u00a0\u00a0\u00a0<\/p><\/td>

\u00a0<\/td><\/tr>
\u00a0<\/td>

5.6 \u2013 Multi Channel Transformer<\/strong>: Remaining Useful Life Estimation through Channel-Independent and Collective Approach<\/strong><\/p>

Paul Nikolian<\/em><\/strong> and Fadi Kurdahi (UC Invine)<\/p><\/td>

\u00a0<\/td><\/tr>
\u00a0<\/td>\u00a0<\/td>\u00a0<\/td><\/tr>

12:30 \u2013 14:00<\/p><\/td>

Networking Lunch<\/strong><\/p><\/td>

\u00a0<\/td><\/tr><\/tbody><\/table>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t
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Registration will be located outside of Sedona<\/strong><\/p>

Registration Hours: 7:00 am – 8:30 am\u00a0<\/p>

Tuesday, June 11<\/u><\/strong><\/p>

All sessions will be held in Sedona<\/p>

Breakfast & Lunch will be located in Salons 7-9<\/p>

Reception will be held in the Orchard Lounge\u00a0<\/p>

Wednesday, June 12 (half day session)<\/u><\/strong><\/p>

Breakout Session #1- Salon A<\/p>

Breakout Session #2- Salon B\u00a0<\/p>

Breakfast and Lunch will be located in Salons 7-9<\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t

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\n\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t","protected":false},"excerpt":{"rendered":"

\/*! elementor – v3.21.0 – 26-05-2024 *\/ .elementor-column .elementor-spacer-inner{height:var(–spacer-size)}.e-con{–container-widget-width:100%}.e-con-inner>.elementor-widget-spacer,.e-con>.elementor-widget-spacer{width:var(–container-widget-width,var(–spacer-size));–align-self:var(–container-widget-align-self,initial);–flex-shrink:0}.e-con-inner>.elementor-widget-spacer>.elementor-widget-container,.e-con>.elementor-widget-spacer>.elementor-widget-container{height:100%;width:100%}.e-con-inner>.elementor-widget-spacer>.elementor-widget-container>.elementor-spacer,.e-con>.elementor-widget-spacer>.elementor-widget-container>.elementor-spacer{height:100%}.e-con-inner>.elementor-widget-spacer>.elementor-widget-container>.elementor-spacer>.elementor-spacer-inner,.e-con>.elementor-widget-spacer>.elementor-widget-container>.elementor-spacer>.elementor-spacer-inner{height:var(–container-widget-height,var(–spacer-size))}.e-con-inner>.elementor-widget-spacer.elementor-widget-empty,.e-con>.elementor-widget-spacer.elementor-widget-empty{position:relative;min-height:22px;min-width:22px}.e-con-inner>.elementor-widget-spacer.elementor-widget-empty .elementor-widget-empty-icon,.e-con>.elementor-widget-spacer.elementor-widget-empty .elementor-widget-empty-icon{position:absolute;top:0;bottom:0;left:0;right:0;margin:auto;padding:0;width:22px;height:22px} \/*! elementor – v3.21.0 – 26-05-2024 *\/ .elementor-heading-title{padding:0;margin:0;line-height:1}.elementor-widget-heading .elementor-heading-title[class*=elementor-size-]>a{color:inherit;font-size:inherit;line-height:inherit}.elementor-widget-heading .elementor-heading-title.elementor-size-small{font-size:15px}.elementor-widget-heading .elementor-heading-title.elementor-size-medium{font-size:19px}.elementor-widget-heading .elementor-heading-title.elementor-size-large{font-size:29px}.elementor-widget-heading .elementor-heading-title.elementor-size-xl{font-size:39px}.elementor-widget-heading .elementor-heading-title.elementor-size-xxl{font-size:59px} Tuesday, 11th June 2024 (SingleTrack) Timeslot Topic Organizer Moderator Speaker Title 7:00 \u2013 8:30 Registration and Breakfast 8:30 \u2013 9:00 Opening Address Jyotika Athavale\u00a0BIO, Yervant Zorian BIO, Dimitris Gizopoulos\u00a0BIO, Amr […]<\/p>\n","protected":false},"author":8,"featured_media":0,"parent":0,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"elementor_header_footer","meta":{"footnotes":""},"class_list":["post-157","page","type-page","status-publish","hentry"],"_links":{"self":[{"href":"https:\/\/ieee-ras.conferences.computer.org\/2024\/wp-json\/wp\/v2\/pages\/157","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/ieee-ras.conferences.computer.org\/2024\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/ieee-ras.conferences.computer.org\/2024\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/ieee-ras.conferences.computer.org\/2024\/wp-json\/wp\/v2\/users\/8"}],"replies":[{"embeddable":true,"href":"https:\/\/ieee-ras.conferences.computer.org\/2024\/wp-json\/wp\/v2\/comments?post=157"}],"version-history":[{"count":0,"href":"https:\/\/ieee-ras.conferences.computer.org\/2024\/wp-json\/wp\/v2\/pages\/157\/revisions"}],"wp:attachment":[{"href":"https:\/\/ieee-ras.conferences.computer.org\/2024\/wp-json\/wp\/v2\/media?parent=157"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}