{"id":216,"date":"2024-05-28T02:13:40","date_gmt":"2024-05-28T02:13:40","guid":{"rendered":"https:\/\/ieee-ras.conferences.computer.org\/2024\/?page_id=216"},"modified":"2024-05-28T02:17:38","modified_gmt":"2024-05-28T02:17:38","slug":"invited_talk_arijit_biswas_bio","status":"publish","type":"page","link":"https:\/\/ieee-ras.conferences.computer.org\/2024\/invited_talk_arijit_biswas_bio\/","title":{"rendered":"Invited_talk_Arijit_Biswas_Bio"},"content":{"rendered":"\t\t<div data-elementor-type=\"wp-page\" data-elementor-id=\"216\" class=\"elementor elementor-216\" data-elementor-post-type=\"page\">\n\t\t\t\t<div class=\"elementor-element elementor-element-c848706 e-flex e-con-boxed e-con e-parent\" data-id=\"c848706\" data-element_type=\"container\" data-e-type=\"container\">\n\t\t\t\t\t<div class=\"e-con-inner\">\n\t\t\t\t<div class=\"elementor-element elementor-element-2b60119 elementor-widget elementor-widget-image\" data-id=\"2b60119\" data-element_type=\"widget\" data-e-type=\"widget\" data-widget_type=\"image.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t<img fetchpriority=\"high\" decoding=\"async\" width=\"169\" height=\"300\" src=\"https:\/\/ieee-ras.conferences.computer.org\/2024\/wp-content\/uploads\/sites\/2\/2024\/05\/Hudson_EMR_Xeon_Architecture_Arijit_Biswas-169x300.jpg\" class=\"attachment-medium size-medium wp-image-217\" alt=\"\" srcset=\"https:\/\/ieee-ras.conferences.computer.org\/2024\/wp-content\/uploads\/sites\/2\/2024\/05\/Hudson_EMR_Xeon_Architecture_Arijit_Biswas-169x300.jpg 169w, https:\/\/ieee-ras.conferences.computer.org\/2024\/wp-content\/uploads\/sites\/2\/2024\/05\/Hudson_EMR_Xeon_Architecture_Arijit_Biswas-576x1024.jpg 576w, https:\/\/ieee-ras.conferences.computer.org\/2024\/wp-content\/uploads\/sites\/2\/2024\/05\/Hudson_EMR_Xeon_Architecture_Arijit_Biswas-768x1365.jpg 768w, https:\/\/ieee-ras.conferences.computer.org\/2024\/wp-content\/uploads\/sites\/2\/2024\/05\/Hudson_EMR_Xeon_Architecture_Arijit_Biswas-864x1536.jpg 864w, https:\/\/ieee-ras.conferences.computer.org\/2024\/wp-content\/uploads\/sites\/2\/2024\/05\/Hudson_EMR_Xeon_Architecture_Arijit_Biswas-1152x2048.jpg 1152w, https:\/\/ieee-ras.conferences.computer.org\/2024\/wp-content\/uploads\/sites\/2\/2024\/05\/Hudson_EMR_Xeon_Architecture_Arijit_Biswas-scaled.jpg 1440w\" sizes=\"(max-width: 169px) 100vw, 169px\" \/>\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t<div class=\"elementor-element elementor-element-0f82da4 e-flex e-con-boxed e-con e-parent\" data-id=\"0f82da4\" data-element_type=\"container\" data-e-type=\"container\">\n\t\t\t\t\t<div class=\"e-con-inner\">\n\t\t\t\t<div class=\"elementor-element elementor-element-f09f8fe elementor-widget elementor-widget-text-editor\" data-id=\"f09f8fe\" data-element_type=\"widget\" data-e-type=\"widget\" data-widget_type=\"text-editor.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t\t\t\t\t<p>Arijit Biswas is a Senior Principal Engineer in the Datacenter Products Architecture group at Intel.\u00a0 He graduated from Carnegie Mellon University in 1997, joining Intel&#8217;s Pentium 4 design team immediately thereafter.\u00a0 During his 25+ year career he has done everything from post-Si debug through circuit design &amp; validation to architecture &amp; micro-architecture.\u00a0 Arijit is technical director of the Technologies for Reliability &amp; Usage group, responsible for developing several marquee technologies such as Turbo Boost Max 3.0 and Xeon reliability architectures to mitigate soft errors &amp; silent data errors.\u00a0 Arijit developed the first architectural vulnerability factor models using analytical methods at Intel, which are now broadly used across the company as well as the industry.\u00a0 In doing so he and his team developed many of the fundamental principles guiding analytical reliability modeling today such as address based AVF.\u00a0 Arijit is currently the chief architect of the Sapphire Rapids &amp; Emerald Rapids Xeon CPUs (4<sup>th<\/sup>\u00a0&amp; 5<sup>th<\/sup>\u00a0Gen Intel Xeon CPUs).<\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t","protected":false},"excerpt":{"rendered":"<p>\/*! elementor &#8211; v3.21.0 &#8211; 26-05-2024 *\/ .elementor-widget-image{text-align:center}.elementor-widget-image a{display:inline-block}.elementor-widget-image a img[src$=&#8221;.svg&#8221;]{width:48px}.elementor-widget-image img{vertical-align:middle;display:inline-block} Arijit Biswas is a Senior Principal Engineer in the Datacenter Products Architecture group at Intel.\u00a0 He graduated from Carnegie Mellon University in 1997, joining Intel&#8217;s Pentium 4 design team immediately thereafter.\u00a0 During his 25+ year career he has done everything from post-Si debug [&hellip;]<\/p>\n","protected":false},"author":4,"featured_media":0,"parent":0,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"elementor_canvas","meta":{"footnotes":""},"class_list":["post-216","page","type-page","status-publish","hentry"],"_links":{"self":[{"href":"https:\/\/ieee-ras.conferences.computer.org\/2024\/wp-json\/wp\/v2\/pages\/216","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/ieee-ras.conferences.computer.org\/2024\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/ieee-ras.conferences.computer.org\/2024\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/ieee-ras.conferences.computer.org\/2024\/wp-json\/wp\/v2\/users\/4"}],"replies":[{"embeddable":true,"href":"https:\/\/ieee-ras.conferences.computer.org\/2024\/wp-json\/wp\/v2\/comments?post=216"}],"version-history":[{"count":0,"href":"https:\/\/ieee-ras.conferences.computer.org\/2024\/wp-json\/wp\/v2\/pages\/216\/revisions"}],"wp:attachment":[{"href":"https:\/\/ieee-ras.conferences.computer.org\/2024\/wp-json\/wp\/v2\/media?parent=216"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}